1. Field of the Invention
The present invention relates generally to clock generating circuitry and, in particular, to circuitry for maintaining the frequency of an output clock when the input clock is lost.
2. Description of Related Art
For wired and wireless network applications, the recovered clock from a serial communications link is typically noisy and needs to be cleaned up by a clock conditioner or clock jitter cleaner. The outputs of a clock conditioner are used to provide low noise clock sources for other system function blocks such as analog to digital converters (ADC), digital to analog converters (DAC), serializer/deserializer devices (SERDES) and the like. In such applications, the input clock to the clock conditioner may be lost due to failures in the communication link such as a broken wire, failure of the SERDES device and the like. When the input clock is lost, it is typically required by the communication system that the clock conditioner maintain precise output frequencies for long periods of time such as several days or even longer.
FIG. 1 shows a typical prior art clock conditioning circuit that is essentially a phase locked loop (PLL). A clock CLKR to be conditioned, sometimes referred as a reference clock, is fed to one input of a phase frequency detector 16. Clock CLKR may be divided down in frequency by a divider 18. A conditioned clock CLKO is fed to a second input of phase detector 16, where an optional frequency divider 20 can also be used. Frequency dividers 18 and 20 allow the frequencies of the two clocks CLKR and CLKO to differ but still be maintained in phase with one another. Phase detector 16 is typically comprised of a pair of D type flip flops with one flip-flop being set by the rising edge of CLKR (or the divided version of CLKR) and the other being set by the rising edge of CLKO (or the divided version of CLKO). Once both flip-flops are set, both are reset at the same time following a small delay. Thus, if the two clocks are in phase, the rising edges will be concurrent so that simultaneous narrow pulses will be produced at the two detector outputs. If the rising edge of CLKR precedes that of CLKO, the pulse width of output UP will be greater than the narrow pulse width of output DN with the difference in duration relating to the time difference of the rising edges. Conversely, if the rising edge of CLKR follows that of CLKO, then the pulse width of output DN will be greater than that of output UP, with the difference in width again being a function of the rising edge time difference.
The two outputs UP and DN are coupled to the respective inputs of a charge pump circuit 22, with circuit 22 including a high side pump component 22A controlled by signal UP and a low side pump component 22B controlled by signal DN. Details of the charge pump circuit 22 are shown in FIG. 2. The high side component 22A includes a current source 34A which can be switched to a pump output 24 by way of a switch 36A controlled by signal UP. The low side component 22B includes a current source 34B which can be switched to the pump output 24 by way a switch 36B controlled by signal DN. The two current sources 36A and 36B are of equal magnitude, with current source 34A sourcing current to output 24 and current source 34B sinking current from the output. As will be described, the output 24 of the charge pump 22 is connected to a low pass filter which operates to essentially integrate the current pulses provided by the charge pump components 22A and 22B.
Returning to FIG. 1, as previously noted, the output of the charge pump circuit is filtered by a low pass filter 26. Filter 26 is typically in the form of a single capacitor connected between output 24 and the circuit common connected in parallel with a series-connected capacitor and resistor combination. Thus, the output of the filter on line 30 is directly connected to the filter input on line 24. The filter output on line 30 is an error or tuning signal which is provided to the control input of the crystal based voltage controlled oscillator (VCXO) 28. As is well known, a voltage controlled oscillator provides an output signal having a frequency which can be varied in response to changes in a control input (tuning signal), with instantaneous changes in frequency corresponding to a change in phase. Oscillator 28 is configured to provide a clock CLKO which it in phase with the reference clock CLKR based upon the magnitude of the input tuning signal. Note that phase noise beyond the PLL loop bandwidth present on clock CLKR is substantially cleaned from clock CLKO.
As previously noted, in the event the reference clock signal CLKR is missing for some reason, many systems require that the clock conditioning circuitry maintain the frequency at the correct value for extended periods of time. One prior art approach is to force the output 24 to a high impedance. FIG. 3 depicts an alternative prior art charge pump circuit 44 which includes an upper component 44A and a lower component 44B. The construction of charge pump 44 is similar to that of charge pump 22 and includes upper and lower current sources 34A and 34B and associated switches 36A and 36B. The alternative charge pump 44 further includes isolation switches 38A and 38B that are closed during normal charge pump operation. In the event of the loss of the reference clock CKLR, a loss of clock detector (not depicted) will generate a hold signal VHO1 which will operate to open switches 38A and 38B thereby isolating the outputs of the charge pump 44 from output line 24/30. The tuning voltage on line 24, at the time of the loss of CKLR will tend to be maintained by the low pass filter which is essentially a capacitance connected between line 24 and ground. Thus, the tuning voltage to the control input to the VCXO on line 24/30 will be held in place so that the frequency output of VCXO 28 is maintained. However, the tuning voltage will change primarily due to leakage currents represented by element 46. These leakage currents may be attributable to the leakage current in the charge pump output, or the VCXO input or leakage through the capacitors of low pass filter 26 and can be on the order of 1 nA or larger. Assuming that the tuning voltage is about 1.65 V (VDD/2 or 3.3V/2) and assuming that the effective capacitance between line 24/30 and ground is about 10 μF, then two hours after the loss of CLKR the tuning voltage will drop by 0.93 volts. Assuming that the frequency gain Kvcxo of VXCO is 100 ppm/V, the output frequency will drift 72 ppm in just two hours.
In order to further reduce the change in frequency after a loss of a reference clock, another prior art approach is to first isolate the output of the charge pump circuit as previously described by opening switches 38A and 38B in response to signal VHO1. In addition, after line 24/30 has been isolated from the charge pump circuit 44 a fixed voltage VDD/2 is applied to line 24/30. Voltage VDD/2, which typically is the nominal VCXO tuning voltage, is provided by a buffer circuit 42 when switch 40 is closed in response to a signal VHO2 which is produced along with signal VHO1 when a loss of the reference clock CLKR is detected. Unfortunately, this approach is not capable of holding an accurate output frequency over changes in supply voltage, ambient temperature and VCXO tuning characteristic variations. For example, lab testing has confirmed that, even when changes in the VCXO tuning characteristics are not considered, the output frequency can vary between −10 ppm and +30 ppm for a typical commercial VCXO when its tuning voltage is held at VDD/2 and the supply voltage is varied between +3.15V and +3.45V and the ambient temperature is varied between −40 C and +85 C.
There is a need for a clock conditioning system which includes a phase locked loop which is capable of accurately maintaining an output clock frequency over extended periods of time after the input or reference clock has been lost. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings, the present invention provides this improved capability.